The present invention relates generally to integrated circuit designs, and more particularly to an electrostatic discharge (ESD) protection circuit having floating diffusion regions to improve ESD performance for protecting the core circuit of an integrated circuit (IC) from damage that may be caused by an ESD event.
The gate oxide of a metal-oxide-semiconductor (MOS) transistor of an IC is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than the supply voltage. It is understood that a regular supply voltage in an integrated circuit is 5.0, 3.3 volts, or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive because the charge and any resulting current are extremely large in the transient. For this reason, it is of critical importance to discharge any static electric charge.
ESD protection circuit is typically added to integrated circuits (ICs) at the bond pads. The pads are the connections to outside circuits, for all electric power supplies, electric grounds, and electronic signals. Such added circuits must allow normal operation of the IC. It means that a protective circuit is effectively isolated from the normally operating core circuit because it blocks current flow through itself to ground, or any other circuit, or pad. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to some pads, and electronic signals generated by the core circuit of the IC are supplied to other pads for delivery to external circuits and devices. In an isolated, unconnected IC, all pads are considered to be electrically floating, or of indeterminate voltage. In most cases, this means the pads are at ground, or zero voltage.
ESD can arrive at any pad. This can happen, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. In an isolated IC, ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when ESD acts as a power supply at a randomly selected pad, the protection circuit acts differently then it does when the IC is operating normally. When an ESD event occurs, the protection circuit must quickly become conductive so that the electrostatic charge is conducted to VSS or ground and is thus dissipated before damaging an internal circuit.
ESD protection circuit, therefore, has two states: normal operation mode and ESD mode. When an IC is in the normal operation mode, the ESD protection circuit appears invisible to the IC by blocking current through itself. In the ESD mode, the ESD protection circuit serves its purpose of protecting the IC by conducting an electrostatic charge quickly to VSS, or ground, before damaging the internal circuit.
However, a typical ESD protection circuit may not be able to dissipate ESD pulses fast enough before damaging charges flow into the internal circuit. This can cause damage to the IC. In order to ensure that protective transistors in the ESD protection circuit turn on before any damage can be done to an IC, the trigger-on voltage of those transistors may need to be adjusted. By lowering the trigger-on voltage, the transistor can turn on much sooner, thus allowing quicker dissipation of the ESD current.
It is always desirable to have faster dissipation of ESD current during an ESD event before harmful charges can damage the IC.